1. Field of the Invention
The present invention relates to a phase synchronization circuit, a one-shot pulse generating circuit and a signal processing system including such phase synchronization circuit and one-shot pulse generating circuit.
2. Description of the Prior Art
In the zone bit recording process of the prior art for information storage media including hard discs, magneto-optial discs and other discs, the frequency of data write clocks varies depending on each zone which includes a plurality of tracks. In the four-zone bit recording, for example, the data write clocks have different frequencies, f1=8 MHz; f2=10 MHz; f3=12 MHz and f4=14 MHz. The zone bit recording process can provide substantially equal recording density for both the outermost and innermost peripheral zones by varying the frequency of the write clocks in the above manner, and thus increase the storage capacity of an information storage medium. When data in the information storage medium in which the writing has been performed according to the zone bit recording process is read out, the transfer rate of the read data corresponds to the write clock frequency of the respective zones. Therefore, a system for recording on or reproducing from such an information storage medium is required to generate clocks corresponding to the frequency of the respective zones, and also to reproduce data read out at the transfer rate corresponding to the frequency of the respective zones.
For example, in a phase synchronization circuit shown in FIG. 22, a phase comparator 307 receives a signal from 1/M frequency divider 302 which divides the reference frequency fm from reference frequency 301 source and a signal 1/N frequency divider 310 which divides the frequency fw of write clocks, and these signals are compared with each other (M and N are natural numbers). A DC voltage depending on the resulting phase difference is then outputted from a filter circuit 308 toward a variable frequency oscillation circuit 309, and controls an oscillation frequency. Thus, clocks corresponding to each zone and having a frequency fw=fm.times.(N/M) can be generated.
For example, Japanese Patent Application Laid-Open No. 59-28209 discloses a two-stage phase synchronization circuit which is provided with first and second phase synchronization circuits including voltage control type variable frequency oscillation circuits that have the same coefficient of voltage/frequency shift. The first phase synchronization circuit is synchronized with the reference frequency. The control voltage of the oscillation circuit in the first phase synchronization circuit is applied directly to the control input of the oscillation circuit in the second phase synchronization circuit. Thus, the free-running frequency of the second phase synchronization circuit becomes equal to the oscillation frequency of the oscillation circuit in the first phase synchronization circuit. According to the prior art, the free-running frequency of the second phase synchronization circuit is not influenced by variabilities in production, power supply voltage, ambient temperature and the other factors when the reference frequency is stable. Therefore, a high-precision and high-stability phase synchronization circuit could be realized without adjustment. Such prior art has been popular as it is extremely effective for unifying oscillation frequencies of oscillation circuits in a plurality of phase synchronization circuits.
In the case where data stored in the information storage medium are read out, the pulse width of the read data is variable. Therefore, it is necessary to provide a circuit called "one-shot pulse generating circuit" (which is referred simply to "one-shot circuit" hereafter) in order to generate pulses with constant width from the read data.
FIG. 23 shows a one-shot circuit constructed according to the prior art, which comprises an input detecting circuit 351 for first detecting the rising edge of an input signal inputted into the input terminal 353 thereof. The output of the input detecting circuit 351 is delayed for a certain time by a delay circuit 355, and the output 352 of the delay circuit 355 is inputted into the reset terminal of the input detecting circuit 351. Thus, the output terminal 354 of the input detecting circuit 351 generates a one-shot pulse.
Further, in the one-shot circuit of FIG. 23, a phase synchronization circuit 359 comprises a variable frequency oscillation circuit (ring oscillator) 360 having the same structure as that of the delay circuit 355 except that the circuit 360 has ring-connected inverters. A common oscillation control signal is inputted into the delay control terminal of the delay circuit 355 and also into the oscillation control terminal of the variable frequency oscillation circuit 360. Thus, the delay time of the delay circuit 355 can be determined depending on the reference frequency.
In such one-shot circuit, since the variable frequency oscillation circuit 360 has the same structure as that of the delay circuit 355 except that the circuit 360 has ring-connected inverters, errors in the delay time of the delay circuit 355 can be always compensated by the common oscillation control signal irrespective of variabilities in production, power supply voltage and ambient temperature. This provides one-shot pulses with improved stability and accuracy.
When the oscillation time pried of desired one-shot pulse width and that of said variable frequency oscillation circuit 360 are relatively close, and when the reference frequency is fixed, such art is technically effective and has been therefore used for one-shot circuits in the data separator for floppy discs.
A monostable multivibrator circuit, which is one example of the prior art one-shot circuits, is described in detail in Japanese Patent Application Laid-Open No. 61-97418.
However, the phase synchronization circuit having a structure as shown in FIG. 22 raises the following problems. Assuming that the range of variable clock frequency is between 10 MHz and 40 MHz, the range of oscillating voltage in the output Vf of the filter circuit 308 is limited, for example, between one volt and four volts in a single 5 V power supply. This requires the variable frequency oscillation circuit 309 to perform in such a way that the oscillation frequency is variable at least 10 MHz with the change in the output voltage Vf by one volt. Further, considering variabilities in production, power supply voltage, ambient temperature and other factors, such performance must be increased to two to three times so that the oscillation frequency is variable between 20 MHz and 30 MHz with the change in the output voltage Vf by one volt. Nevertheless, when the ratio of oscillation voltage to oscillation frequency (or oscillation current to oscillation frequency) in the variable frequency oscillation circuit 209 is too large, the circuit 309 is inclined to be unlocked or locked incorrectly in phase synchronization, or to increase the jitter due to noises or the like. Thus, the phase sychronization circuit of FIG. 22, has a problem of being unable to increase the variable range of write clocks greatly due to such limitations as inability to increase the above-identified ratio greatly and limits set on the range of oscillating voltage in the filter circuit.
The two-stage phase synchronization circuit shown in Japanese Patent Application Laid-Open No. 59-28209 also raises the following problems. When the oscillation frequency required by the zone bit recording process or the like in the phase synchronization circuit is different from that of the phase synchronization circuit synchronized with the reference frequency, the phase synchronization circuit cannot be used as far as its operational principle is concerned. This results from the fact that the oscillation control terminals cannot be connected to each other since the oscillation circuit differs in oscillation frequencies also differs in oscillation control voltages.
The prior art one-shot circuit shown in FIG. 23 further raises the following problems when the one-shot pulse width is much longer than the oscillation period of the variable frequency oscillation circuit 380, and when reference frequency should be varied in a wider range.
The prior art one-shot circuit set the desired one-shot pulse width by the delay time of the inverter in the delay circuit 355. To provide a longer one-shot pulse width, the number of delay inverter stages must be increased. This resulted in increasing the chip area and manufacturing cost. Further, although the delay circuit 355 is similar in structure to the variable frequency oscillation circuit 380 in the phase synchronization circuit, they are essentially different in functions and characteristics. Therefore, when a common oscillation control signal is inputted into the delay control terminal of the delay circuit 355 and also into the oscillation control terminal of the variable frequency oscillation circuit 360, the inverter delay time of the variable frequency oscillation circuit 360 is not completely identical to that of the delay circuit 355. Particularly, when the reference frequency is changed for controlling the delay time in a wide range, it is impossible to make the delay times of the circuit 355 and the circuit 360 equal within the entire frequency range.
When the relationship between the oscillation frequency of the variable frequency oscillation circuit 360 and the delay time of the delay circuit is changed, the delay characteristics of the delay circuit must be varied since the common oscillation control signal is used. As a result, the identical characteristics Between the variable frequency oscillation circuit 360 and the delay circuit 355 are further reduced.